Fraunhofer IIS: System on Chip (SoC) Verification Engineer (all genders)

For a technologically more independent Europe, we aim to develop Fraunhofer IIS into a European IC Design Center for trusted and energy-efficient high-speed ICs by 2026. As a leading competence center for digital chip design, we deliver essential cutting-edge technologies in the areas of exascale high-performance computing and trusted electronics. In addition, we offer sophisticated digital design services based on RISC-V. Our target customers are design houses, semiconductor manufacturers, SMEs, and system integrators. Potential applications are areas such as high-speed data processing, blockchain or cybersecurity. Today, our »Integrated Digital Systems« business unit develops digital circuits in CMOS technologies as System on Chip, ASIC or IP.

Here's how you will make a difference

As a SoC Verification Engineer, you will play a key role in pre-silicon RTL verification of block and top-level SoC designs utilizing RISC-V architecture. Working closely with cross-functional teams, you will help shape a modern, reusable verification environment using state-of-the-art methodologies and metric-driven approaches.

Your key responsibilities:

• Understand the nuances of RISC-V architectures and industry-standard low-power architectures to build block/chip level testbenches using best-in-class verification methodologies

• Translate design specifications into comprehensive verification plans in collaboration with system architects

• Develop and maintain reusable testbenches for IP/block-level verification and support IP integration verification

• Create smart, constraint-random and directed test cases tailored to RISC-V SoCs

• Build and analyze coverage models, and refine tests to close coverage gaps

• Debug test failures, manage bug tracking, and ensure coverage closure

• Lead verification reviews to uphold coding quality and best practices in SoC verification

• Prepare, run, and evaluate regression runs

What you bring to the table

• University degree in (electrical) engineering, IT/computer science or another related field

• Solid understanding of digital logic design and RISC-V-based SoC architecture

• Proven experience with SystemVerilog and UVM-based verification environments

• Very good English and good German language skills

• Proactive and independent mindset

Nice to have

• Familiarity with C / C++ programming, assembly and object-oriented languages such as Python

• Knowledge of industry-standard interfaces and bus protocols (e.g., AXI)

• Experience with IP verification methods, integration verification specific to RISC-V and embedded CPU verification

• Interest in low power verification techniques and formal verification tools (e.g. JasperGold)

The position is initially limited to 2 years with the aim to extend it subsequently. The weekly working time is 39 hours. The position can also be filled on a part-time basis with a preference, however, to have it filled as close to a full-time position as possible.

For more information please refer to: https://iisfraunhofer.softgarden.io/job/55713662?l=de